This invention concerns such a data transmission bus in plug-in unit and rack systems wherein plug-in units are connected to the bus when pushed into the rack, so that the plug-in units can be in data transmission connection with one another through the bus.
Relatively complex distributed equipment environments, such as telecommunication equipment and computer systems, use different backplane buses, the purpose of which is to connect the different units electrically and mechanically to each other and to allow prompt communication between the units. The buses may be passive buses or they may be active ones, wherein the peripheral logic speeds up voltage level changes in the bus and thus makes the bus operate faster.
Backplane buses may also be used in systems formed by several hardware racks, such as e.g. in the node device of a digital telecommunication system, where data and clock signals must be transmitted between hardware racks. For timing, digital systems need synchronising signals commonly called clocks. E.g. in such backplane bus systems wherein exactly simultaneous timing information is required, distribution of clocks is carried out in the way shown in FIG. 1 by constructing a star-like transmission line network containing several parallel transmission lines 11 of equal length. For each transmission line there is the line""s own transmitter 12, to which the clock is supplied from a clock source 13 common to all transmission lines. At the end of each transmission line there is the line""s own receiver 14 for reception of the clock. Drawbacks of this kind of solution (caused by several parallel transmitter/receiver couples) are relatively high costs and difficult implementation of the construction among other equipment, e.g. inflexibility in situations where changes occur. For example, the place of an individual transmitter can not be moved anywhere in practice, because cabling can not be drawn from anywhere so that the transmission lines will be of equal length.
If exactly simultaneous timing information is not a necessary feature, Bus Transceiver Logic (BTL) circuits have been used in backplane buses e.g. in a structure according to the Futurebus standard, wherein one transmitter supplies a common bus to which several receivers are connected. A first drawback of this solution is that propagation delays are different with different receivers. Under these circumstances, the timing information is not sufficiently exact for all applications, but the solution is suitable in those cases only where exactly simultaneous timing information is not a necessary feature. In addition, the power consumption is high in the system due to parallel termination at both ends of the bus.
Due to increasing clock frequencies and a growing complexity of the equipment, backplane buses have become one of the major factors limiting system performance. If those parameters which are critical to the backplane bus, that is, delay, noise and noise tolerance, are poorly predicted, then the performance determined for the system will not be achieved. The specific impedance of the backplane bus is an important factor affecting system performance and design. It affects important parameters such as propagation delay, noise tolerance, connection noise, internal capacitance and cross-talk. In theory, the specific impedance will not affect the propagation delay of a signal propagating on the bus, but taking into account those capacitances of equipment connected to the bus which connect in parallel with the specific impedance and thus increase the total impedance, a slower bus operation will result.
With a reduced specific impedance the internal bus capacitance and thus the signal rise time will grow. A rise time delay is thus mainly caused by the backplane bus, but it is also caused by the charging delay of plug-in unit controllers connected to the backplane bus which increases the total delay.
FIG. 2 shows a bus B, which is located in the rear part of an equipment cabinet and to which N plug-in units are connected through transmitter/receiver blocks. The bus end mounts a plug-in unit supplying such a master clock to the bus with which the other plug-in units of the bus will synchronise. Due to the grounds mentioned above, the bus has a certain clock frequency so that at frequencies exceeding this delays will grow so much that unit C, which is located at the other end of the bus and to which unit A at the opposite end sends a signal in its transmission time slot, will receive the signal so late that a part of the signal or the whole signal will drift outside the reception time slot.
By using a quick bus interface in the plug-in units, so-called GTL technology, the bus clock frequency may be increased to some extent. The Gunning Transceiver Logic (GTL) using Low-Voltage-Swing (LVS) CMOS transistors has been developed especially to allow integration of transmitter/receiver for Very Large-Scale Integration (VLISI) and ASIC circuits instead of the transmitter/receiver being a separate module as in traditional plug-in units. By using GTL technology a maximum number of ten plug-in units may be connected to the passive bus B located in the rear part of the equipment cabinet.
When using GTL technology, the transmitter/receiver capacitance of the plug-in unit is approximately 10-15 pF. When plug-in units are added so that their number is more than ten, the result is that the bus impedance will vary between 25 and 80xcexa9, whereby the bus is never fully adapted. In consequence, when the clock pulse amplitude has risen, there will be oscillation caused by interference in the signal, and the units will have to wait until the oscillations have passed by.
It should also be noticed that the master clock located at one end of the bus will cause phase skew of the clock on the long bus.
One solution of problems caused by transmission delays is presented in the applicant""s Finnish Patent Application FI-953010, inventor Voutilainen Martti. The idea there is to supply a step-less essentially sinusoidal waveform to the bus through such an adapter circuit which besides adapting the level of the propagating wave essentially at the desired level, also absorbs the reflection returning from the transmission line and at the same time prevents multiple reflections. Such a waveform similar to a standing wave is hereby obtained in the transmission line, which is formed as the sum of the propagating and once reflected wave and which may be used for system timing and also for information transmission. With the method it is possible in practice to eliminate almost entirely that timing difference between different receivers which is caused by propagation delay.
FIG. 3 shows a system in accordance with the patent application mentioned above in its simplest embodiment. Series resistor R1 is connected to the output of low output impedance sine wave generator 31 so that its opposite pole is connected to transmission line 32, to which receivers 33 of the individual equipment units are connected at different points. Of the individual equipment units ( e.g. of the backplane""s plug-in units) the figure shows only the receiver, because equipment units may be of very many different types and because the structure of the equipment unit does not belong within the scope of the invention. The value of series resistance R1 is essentially the same as the effective impedance of the transmission line, that is, the transmission line impedance in the loaded state (receiver circuits connected to the transmission line). The transmission line end is open and, in addition, the length of the transmission line is shorter than one-fourth of the wave length. In the most advantageous case the transmission line length is approximately equal to xe2x85x9th of the wave length. The receivers are hereby in an area where the amplitude of the transmission line signal is close to its maximum, irrespective of where they are located on the transmission line. If the transmission line length is close to one-fourth of the wave length, then also the receiver closest to the input end is preferably located at a sufficient distance (approximately at a distance of xe2x85x9th of the wave length) from the input point, so that the signal amplitude will be sufficient at the said point.
The propagation delay of the clock can also be compensated for in different ways. It is hereby possible to raise the clock frequency to be used. The Canadian Patent CA-1 301 261, Grover, describes a manner where compensation is performed independently in each plug-in unit or module connected to the bus. Each module contains a clock generator implemented with an analog PLL circuit and all locked to the same common time reference. The arrangement is as follows: a main clock at one end of the bus sends clock pulses to the outgoing line. A return line is in parallel with the line. The line ends remote from the main clock are combined with each other and that end of the return line which is on the main clock side is terminated so that no reflection will occur. Each module is connected both to the outgoing line and at the same point to the return line. When the main clock sends a clock pulse to the outgoing line, the module will identify the pulse edge when it arrives at the module. The pulse propagates to the end of the outgoing line and returns along the return line towards the main clock. The module identifies the edge of the returning pulse as the pulse arrives at the module. The module now knows the exact time between the outgoing and returning pulses. One-half of this time is equal to the module""s time distance from the end of the lines. Each module thus knows its time distance from the end of the lines. When a new clock pulse passes by each module, they will in response to the passing-by generate a synchronisation pulse for their respective clock circuit exactly after one-half of the time measured by the module in question. The clock pulse has hereby propagated to the end of the outgoing line. Each module thus generates a synchronisation pulse exactly at the same moment. The clock of each module will hereby be locked to the same time reference, which thus is the moment when the clock pulse of the main clock has propagated to the end of the outgoing line.
When the clock pulse returns along the return line, the module measures the time between outgoing and returning pulses and after one-half of this time it again generates a synchronisation pulse, and the time measurement begins from that moment at which the following clock pulse has passed by the module. The process described above is repeated constantly, whereby the synchronisation pulse of the module""s clock circuit is always updated when the main clock pulse has propagated to the end of the outgoing line.
The compensation methods work rather well, but they suffer from the necessary extra cabling and time measurement. This increases costs, which is not acceptable in many cases. By making the bus active, added speed is obtained, but its operation in a trouble situation is a drawback: should an active component break down, then the entire bus must be exchanged.
This invention aims at such a backplane bus especially for equipment cabinets which makes it possible to increase the transmission capacity of the passive bus and this way considerably to increase the number of plug-in units connected to the bus without any such compensations for propagation delay of the clock which would increase costs.
The established objective is achieved with the definitions given in the independent claims.
A passive backplane bus is divided physically into two buses, preferably at the midpoint of the bus. The buses are combined to form one logical bus by bridging, but in such a way that the bridging function is not performed on the bus but on a plug-in unit performing bridging functions and connected to the bus at the breaking point. The plug-in unit will make sure that when a plug-in unit located in the first half of the bus sends to a plug-in unit located in the second half of the bus, the transmission time slot will be properly mapped into the transmission time slot of the plug-in unit in the second half and vice versa. Hereby the time slot in the first half and the target time slot in the second half will form a logical channel, which can be allocated on the same principles as for a channel of one time slot.
In order not to waste plug-in unit slots merely on the bridging function, it is advantageous to locate bridging functions on a master unit, which is the telecommunications unit performing an active function which provides the bus with the master clock. It is especially advantageous to locate the bridging function on two plug-in units, whereby if one fails then the other plug-in unit is able to perform the bridging function, thus making sure that the bus will work without any interruption.
Although bridging causes delay in the communications between the different halves, this is not harmful, because the delay is similar for all connections.